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Maxim Integrated Off Campus Drive 2022 | Apply Now

Maxim Integrated Off Campus Drive 2022 Hiring For Engineer Trainee | BE/ B.Tech/Msc | Gandhinagar Location | Apply Now

Maxim Integrated Off Campus Drive 2022 hiring freshers as Graduate Engineer from BE/ B.Tech  /Msc graduates at Gandhinagar . The detailed eligibility and application process are given below.

Recruitment :

Company Name : Maxim Integrated

Job Role: Yield Engineer

Qualification: BE /B.Tech/Msc

Experience: Fresher /0-2 years Experience


Salary :Best In Industry

Job Location: Gandhinagar

Last Date: ASAP


Job Description:

  • Basic understanding of semiconductor manufacturing process, E-Test/WAT and design concepts
  • .Define and maintain relevant matrixes for product performance, reliability, and yield.
  • .Analyze semiconductor yield for patterns and signatures.
  • .Generate and maintain SPC charts for excursion detection and control.
  • .Look out for possible excursions during wafer processing
  • .Real Time analysis of Inline fab data on defects, tool status, commonality and root cause analysis, ETest and WAT related parameters and wafer sort parameters which might not limited from design, circuit blocks to test
  • .Required to be hands-on in day-to-day analysis of information, evaluation and understanding ofdefectmechanisms, ETest/WAT parameter, wafer sort test and design concepts with the mindset of making a difference.
  • Perform root cause analysis for low yields using various advanced data analysis tools
  • Statistical and root cause analysis of sort test and parametric test data.
  • Should be willing to work with flexible timings which can over-lap global time zones.
  • Regular interaction with remote/global teams for projects and resolving yield issues.
  • Own product/product line/technology to improve product/technology health and disposition of hold material with highest accuracy and within target.
  • Identify systematic issues and D0/Cpk/yield opportunity and drive them to fix
  • .Connect failure at Etest/WAT or wafer sort to inline/defect modes with driving fixIdentify design and test issues and work closely with design and test floor for fix.


Skill Set

  • Excellent knowledge of basic science concepts in physics, chemistry, and electronics
  • Basic knowledge of Fab yield, product development, validation, design, assembly, and test engineering
  • Good knowledge of CMOS device physics (desirable) and basic electronics
  • Excellent written and verbal English communication skills
  • Good knowledge of MS office tools
  • Knowledge of semiconductor wafer fabrication process (desirable)
  • Should possess good inter-personal skills
  • Problem solving and analytical skills
  • Result-orientation and attention to details
  • Experience in semiconductor manufacturing/testing, yield engineering or statistical processes domain is an added advantage
  • Person should be willing to work in flexible timings (including night shifts) and flexible weekday (including Saturday and Sunday)
  • Good team player and can smoothly work with cross functional team across the globe


Desired Candidate Profile

Experience: BE/BTech/ME/MTech (Electronics/ Electrical/ Instrumentation), MSc (Physics or Electronics) from a reputed institute with 7+ CGPA aggregate score. Preferred work experience in any industrial domain for around 0-2 years. Work experience in allied domains like LED, Solar and CMOS research/projects will be given preference.
Work Experience:
Pay Rate Type :Salary
Eligible for Relocation: No
Eligible for Work Visa Sponsorship: No
This position may require a deemed export control license for compliance with applicable laws and regulations including but not limited to US Government International Traffic in Arms Regulations (ITAR), US Export Administration Regulations (EAR), or US Treasury Regulation

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